A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files are used to produce patterns called masks by an optical or electron beam pattern generator. Subsequently, during fabrication of the IC, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the IC are therefore formed on the wafer in accordance with the patterns.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then tests and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification are performed to ensure that the integrated circuit layout will perform as desired. Extraction is the process of analyzing the geometric layout and material composition of an integrated circuit layout in order to “extract” the electrical characteristics of the designed integrated circuit layout. The step of verification uses the extracted electrical characteristics to analyze the circuit design using circuit analysis tools.
In modern design and extraction systems, component parameters for a transistor are defined by only a few theoretical geometric properties, such as length (L), width (W), area of source (AS) and area of drain (AD) and in some cases other relatively simplistic geometric properties of the transistor. These identified theoretical geometric properties are then used to determine electrical characteristics and/or the theoretical geometric properties are calculated based on required electrical properties for the transistor.
To test an integrated circuit layout, the integrated circuit designer ‘extracts’electrical characteristics or geometric properties from the integrated circuit layout using an extraction application program. Then, the integrated circuit designer analyzes and possibly simulates the integrated circuit using the extracted electrical characteristics or geometric properties. If the analysis or simulation shows undesired operation of the integrated circuit, then the layout of the integrated circuit must be changed to correct the undesired operation. In addition, the analysis or simulation may also be used to determine the power consumption or operating speed of the integrated circuit. The analysis or simulation may therefore be used in conjunction with the design phase to optimize or the performance of the integrated circuit by adjusting the power consumption or speed.
One problem with conventional EDA tools that perform extraction is that they do not adequately address manufacturing effects that may occur during fabrication of the IC product. In particular, conventional EDA tools that perform extraction cannot adequately address the deviations that exist between the intended and regular-featured geometric shapes that are designed for the IC product, and the non-regular-featured geometric shapes that actually result from combination of OPC, mask making, lithographic, deposition, and etching processes (collectively referred to as the manufacturing process).
The actual shape of a circuit component may differ from the desired shape based on at least two factors. Firstly, neighboring components may affect the shape of a circuit component, because of spacing rules that are used to minimize interactions between components and take the limitations of the lithographic process into account. These are systematic variations that can in theory be determined from the design, for example, by examining the surrounding polygons. Secondly, random variations can affect the shape of a circuit component. Random variations are not determined by the environment, but instead by random factors, such as local variations in the photo-resist, that are not under the designer's control.
Many properties of transistors, such as leakage current, power usage, yield, capacitance, and timing, are dependent on the shape of the transistor. Because many modern systems use a simplistic transistor model, in which the transistors are assumed to be rectangular in shape, extraction and analysis can misestimate these properties of the transistors. As a result, analysis and testing may give an inaccurate representation of the integrated circuit.
These problems are further exacerbated by modern circuit design and manufacturing processes, in which surface area on an IC chip has become one of the most critical design factors. As designers and manufactures are forced to squeeze more and more circuitry onto less and less space, spacing of components on the circuits has reduced significantly. As component spacing is reduced, interactions between components is increased and in particular, the geometry of individual components can be impacted by the component's neighboring components, thus impacting electrical parameters. Levels of imperfections and error percentages that were insignificant and acceptable in older designs with the larger feature sizes and spacing have now become problematic and much more significant for modern designs having much smaller feature sizes and smaller spacing. Modern design and analysis systems and tools cannot accurately account for such geometric impacts. Therefore, what is needed is a method and system for using physically appropriate component models for extraction of electrical parameters.